KAD5512HP-17Q72【PDF 26/34 页】IC ADC 12BIT 170MSPS SGL 72-QFN

您好，
买卖IC网欢迎您。
请登录
免费注册

Sheet目录2002

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6808.3

October 1, 2009

SNR and SINAD are either given in units of dB when the

power of the fundamental is used as the reference, or dBFS

(dB to full scale) when the converter’s full-scale input power

is used as the reference.

Spurious-Free-Dynamic Range (SFDR) is the ratio of the

RMS signal amplitude to the RMS value of the largest

spurious spectral component. The largest spurious spectral

component may or may not be a harmonic.

Revision History

DATE

REVISION

CHANGE

7/30/08

Rev 1

Initial Release of Production Datasheet

10/29/08 FN6808.0 Converted to intersil template. Assigned file number FN6808. Rev 0 - first release (as preliminary datasheet) with new file

number.

12/5/08

FN6808.0 Applied Intersil Standards

1/13/09

FN6808.1 P1; revised Key Specs. Features - 1st bullet; changed 2.5dB to 2.2dB

P2; added Part Marking column to Order Info

P4; Moved Thermal Impedance under Thermal Info (used to be on p. 8). Added Theta JA Note 3.

P4-6; edits throughout the Elec Specs table. Revised Note 6.

P6; Revised Digital Specs table (added VIH, VIL specs)

P8; added Notes 9-10 to Switching Specs table. Removed ESD section

P13-15; revised Performance Curves throughout

P16; Functional Description section; revised 6th sentence of 1st paragraph

P17; User Initiated Reset section; revised 2nd sentence of 1st paragraph

P20; SPI section; revised 4th sentence of 1st paragraph

P22; SPI Physical Interface; revised 2nd sentence of 4th paragraph

P23; added last 2 sentences to 1st paragraph of "ADDRESS 0X24: GAIN_FINE". Revised Table 8

P24; revised last 2 sentence of "ADDRESS 0X71: PHASE_SLIP". Removed Figure of "PHASE SLIP: CLK÷2 MODE, fCLOCK

= 500MHz"

P27; revised Figure 45, Table 17; revised Bits7:4, Addr C0

Throughout; formatted graphics to Intersil standards

2/25/09

FN6808.2 Changed “odd” bits N in Figure 1A - DDR to “even” bits N, Replaced POD L48.7x7E due to changed dimension from “9.80 sq”

to “6.80” sq. in land pattern

5/29/09

FN6808.3 1) Added nap mode, sleep mode wake up times to spec table

2) Added CSB, SCLK Setup time specs for nap, sleep modes

3) Added section showing 72pin/48pin package feature differences and default state for clkdiv, outmode, outfmt page 30

4) Changed SPI setup time specs wording in spec table

5) Added ‘Reserved’ to SPI memory map at address 25H

6) Renumbered Notes

7) Added test platform link on page 31

8) Added DDR enable Note 13 for 48 pin/72 pin options

9) Changed pin description table for 72/48 pin option, added DDR notes

10) Changed multi device note in SPI physical interface section to show 3-wire application.page 23

11) Updated digital output section for DDR operation page 20

12) Change to Figures 23 and 24 and description in text

13) Added connect note for thermal pad

14) Formatted Figures 25 and 26 with Intersil Standards,

15) Added Pb-free reflow link, Over-temp reference in Min and Max and Note

08/19/09

16) Updated sleep mode Power spec

17) Change to SPI interface section in spec table, timing in cycles now, added write, read specific timing specs.

18) Updated SPI timing diagrams, Figures 35, 36

19) Updated wakeup time description in “Nap/Sleep” on page 21.

20) Removed calibration note in spec table

21) Updated cal paragraph in user initiated reset section per DC.

9/3/09

22) Removed “ADDRESS 0X70: SKEW_DIFF” and associated Table 11 from page 25.

23) Modified Note 4 from: "Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified.

Temperature limits established by characterization and are not production tested."

to: "Parameters with Min and/or MAX limits are 100% production tested at their worst case temperature extreme ( +85C)."

24) Removed reference to Note 7 in digital and switching specification table headers (Note 7 reads "The DLL Range setting

must be changed for low speed operation. See Table 14 on page 26."

KAD5512HP

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式